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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. march 1992 copyright ? intel corporation, 1995 order number: 240448-005 intel387 tm dx math coprocessor y high performance 80-bit internal architecture y implements ansi/ieee standard 754- 1985 for binary floating-point arithmetic y expands intel386 tm dx cpu data types to include 32-, 64-, 80-bit floating point, 32-, 64-bit integers and 18-digit bcd operands y directly extends intel386 tm dx cpu instruction set to include trigonometric, logarithmic, exponential and arithmetic instructions for all data types y upward object-code compatible from 8087 and 80287 y full-range transcendental operations for sine, cosine, tangent, arctangent and logarithm y built-in exception handling y operates independently of real, protected and virtual-8086 modes of the intel386 tm dx microprocessor y eight 80-bit numeric registers, usable as individually addressable general registers or as a register stack y available in 68-pin pga package y one version supports 16 mhz 33 mhz speeds (see packaging spec: order y 231369) the intel387 tm dx math coprocessor (mcp) is an extension of the intel386 tm microprocessor architecture. the combination of the intel387 dx mcp with the intel386 tm dx microprocessor dramatically increases the processing speed of computer application software which utilize mathematical operations. this makes an ideal computer workstation platform for applications such as financial modeling and spreadsheets, cad/cam, or graphics. the intel387 dx math coprocessor adds over seventy mnemonics to the intel386 dx microprocessor instruc- tion set. specific intel387 dx mcp math operations include logarithmic, arithmetic, exponential, and trigono- metric functions. the intel387 dx mcp supports integer, extended integer, floating point and bcd data formats, and fully conforms to the ansi/ieee floating point standard. the intel387 dx math coprocessor is object code compatible with the intel387 sx mcp, and upward object code compatible from the 80287 and 8087 math coprocessors. object code for intel386 dx/intel387 dx is also compatible with the intel486 tm microprocessor. the intel387 dx mcp is manufactured on 1 micron, chmos iv technology and packaged in a 68-pin pga package. 240448 1 figure 0.1. intel387 tm dx math coprocessor block diagram 1
intel387 tm dx math coprocessor contents page 1.0 functional description 5 2.0 programming interface 6 2.1 data types 6 2.2 numeric operands 6 2.3 register set 8 2.3.1 data registers 8 2.3.2 tag word 8 2.3.3 status word 9 2.3.4 instruction and data pointers 12 2.3.5 control word 14 2.4 interrupt description 14 2.5 exception handling 15 2.6 initialization 15 2.7 8087 and 80287 compatibility 16 2.7.1 general differences 16 2.7.2 exceptions 17 3.0 hardware interface 17 3.1 signal description 17 3.1.1 intel386 tm dx cpu clock 2 (cpuclk2) 20 3.1.2 intel387 tm dx mcp clock 2 (numclk2) 20 3.1.3 intel387 tm dx mcp clocking mode (ckm) 20 3.1.4 system reset (resetin) 21 3.1.5 processor extension request (pereq) 21 3.1.6 busy status (busy y ) 21 3.1.7 error status (error y ) 21 3.1.8 data pins (d31 d0) 21 3.1.9 write/read bus cycle (w/r y ) 21 3.1.10 address strobe (ads y ) 21 3.1.11 bus ready input (ready y ) 22 3.1.12 ready output (readyo y ) 22 3.1.13 status enable (sten) 22 3.1.14 mcp select y 1 (nps1 y ) 22 3.1.15 mcp select y 2 (nps2) 22 3.1.16 command (cmd0 y ) 22 2 2
contents page 3.2 processor architecture 22 3.2.1 bus control logic 23 3.2.2 data interface and control unit 23 3.2.3 floating point unit 23 3.3 system configuration 23 3.3.1 bus cycle tracking 24 3.3.2 mcp addressing 24 3.3.3 function select 24 3.3.4 cpu/mcp synchronization 24 3.3.5 synchronous or asynchronous modes 25 3.3.6 automatic bus cycle termination 25 3.4 bus operation 25 3.4.1 nonpipelined bus cycles 26 3.4.1.1 write cycle 26 3.4.1.2 read cycle 26 3.4.2 pipelined bus cycles 27 3.4.3 bus cycles of mixed type 28 3.4.4 busy y and pereq timing relationship 28 4.0 electrical data 30 4.1 absolute maximum ratings 30 4.2 dc characteristics 30 4.3 ac characteristics 31 5.0 intel387 tm dx mcp extensions to the intel386 tm dx cpu instruction set 36 appendix aecompatibility between the 80287 mcp and the 8087 a-1 figures figure 0.1 intel387 tm dx math coprocessor block diagram 1 figure 1.1 intel386 tm dx microprocessor and intel387 tm dx math coprocessor register set 5 figure 2.1 intel387 tm dx mcp tag word 8 figure 2.2 mcp status word 9 figure 2.3 protected mode intel387 tm dx mcp instruction and data pointer image in memory, 32-bit format 12 figure 2.4 real mode intel387 tm dx mcp instruction and data pointer image in memory, 32- bit format 13 figure 2.5 protected mode intel387 tm dx mcp instruction and data pointer image in memory, 16-bit format 13 figure 2.6 real mode intel387 tm dx mcp instruction and data pointer image in memory, 16- bit format 13 figure 2.7 intel387 tm dx mcp control word 14 figure 3.1 intel387 tm dx mcp pin configuration 19 3 3
contents page figures (continued) figure 3.2 asynchronous operation 20 figure 3.3 intel386 tm dx microprocessor and intel387 tm dx mcp coprocessor system configuration 23 figure 3.4 bus state diagram 25 figure 3.5 nonpipelined read and write cycles 27 figure 3.6 fastest transitions to and from pipelined cycles 28 figure 3.7 pipelined cycles with wait states 29 figure 3.8 sten, busy y and pereq timing relationship 29 figure 4.0a typical output valid delay vs load capacitance at max operating temperature 32 figure 4.0b typical output rise time vs load capacitance at max operating temperature 32 figure 4.1 cpuclk2/numclk2 waveform and measurement points for input/output a.c. specifications 33 figure 4.2 output signals 33 figure 4.3 input and i/o signals 34 figure 4.4 reset signal 34 figure 4.5 float from sten 34 figure 4.6 other parameters 35 tables table 2.1 intel387 tm dx mcp data type representation in memory 7 table 2.2 condition code interpretation 10 table 2.3 condition code interpretation after fprem and fprem1 instructions 11 table 2.4 condition code resulting from comparison 11 table 2.5 condition code defining operand class 11 table 2.6 intel386 tm dx microprocessor interrupt vectors reserved for mcp 15 table 2.7 exceptions 16 table 3.1 intel387 tm dx mcp pin summary 18 table 3.2 intel387 tm dx mcp pin cross-reference 18 table 3.3 output pin status after reset 21 table 3.4 bus cycles definition 24 table 4.1 dc specifications 30 table 4.2a combinations of bus interface and execution speeds 31 table 4.2b timing requirements of the execution unit 31 table 4.2c timing requirements of the bus interface unit 31 table 4.3 other parameters 35 4 4
intel387 tm dx math coprocessor intel386 tm dx microprocessor registers general registers 31 15 0 eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl esi si edi di ebp bp esp sp segment registers 15 0 cs ss ds es fs gs 31 0 eip eflags l intel387 tm dx mcp data registers l tag field l 79 78 64 63 0 1 0 l l r0 sign exponent significand l r1 l r2 l l r3 l r4 l r5 l l r6 l r7 l l l 15 0 47 0 l control register instruction pointer (in i386 tm dx cpu) l status register data pointer (in i386 tm dx cpu) l l tag word l l l l l figure 1.1. intel386 tm dx microprocessor and intel387 tm dx math coprocessor register set 1.0 functional description the intel387 tm dx math coprocessor provides arithmetic instructions for a variety of numeric data types in intel386 tm dx microprocessor systems. it also executes numerous built-in transcendental functions (e.g. tangent, sine, cosine, and log func- tions). the intel387 dx mcp effectively extends the register and instruction set of a intel386 dx micro- processor system for existing data types and adds several new data types as well. figure 1.1 shows the model of registers visible to programs. essentially, the intel387 dx mcp can be treated as an additional resource or an extension to the intel386 dx micro- processor. the intel386 dx microprocessor togeth- er with a intel387 dx mcp can be used as a single unified system. the intel387 dx mcp works the same whether the intel386 dx microprocessor is executing in real-ad- dress mode, protected mode, or virtual-8086 mode. all memory access is handled by the intel386 dx microprocessor; the intel387 dx mcp merely oper- ates on instructions and values passed to it by the intel386 dx microprocessor. therefore, the intel387 dx mcp is not sensitive to the processing mode of the intel386 dx microprocessor. in real-address mode and virtual-8086 mode, the in- tel386 dx microprocessor and intel387 dx mcp are completely upward compatible with software for 8086/8087, 80286/80287 real-address mode, and intel386 dx microprocessor and 80287 coproces- sor real-address mode systems. in protected mode, the intel386 dx microprocessor and intel387 dx mcp are completely upward com- patible with software for 80286/80287 protected mode, and intel386 dx microprocessor and 80287 coprocessor protected mode systems. the only differences of operation that may appear when 8086/8087 programs are ported to a protect- ed-mode intel386 dx microprocessor and intel387 dx mcp system ( not using virtual-8086 mode), is in the format of operands for the administrative instruc- tions fldenv, fstenv, frstor and fsave. these instructions are normally used only by excep- tion handlers and operating systems, not by applica- tions programs. the intel387 dx mcp contains three functional units that can operate in parallel to increase system per- formance. the intel386 dx microprocessor can be transferring commands and data to the mcp bus control logic for the next instruction while the mcp floating-point unit is performing the current numeric instruction. 5 5
intel387 tm dx math coprocessor 2.0 programming interface the mcp adds to the intel386 dx microprocessor system additional data types, registers, instructions, and interrupts specifically designed to facilitate high- speed numerics processing. to use the mcp re- quires no special programming tools, because all new instructions and data types are directly support- ed by the intel386 dx cpu assembler and compilers for high-level languages. all 8086/8088 develop- ment tools that support the 8087 can also be used to develop software for the intel386 dx microproc- essor and intel387 dx math coprocessor in real-ad- dress mode or virtual-8086 mode. all 80286 devel- opment tools that support the 80287 can also be used to develop software for the intel386 dx micro- processor and intel387 dx math coprocessor. all communication between the intel386 dx micro- processor and the mcp is transparent to applica- tions software. the cpu automatically controls the mcp whenever a numerics instruction is executed. all physical memory and virtual memory of the cpu are available for storage of the instructions and op- erands of programs that use the mcp. all memory addressing modes, including use of displacement, base register, index register, and scaling, are avail- able for addressing numerics operands. section 6 at the end of this data sheet lists by class the instructions that the mcp adds to the instruction set of the intel386 dx microprocessor system. 2.1 data types table 2.1 lists the seven data types that the intel387 dx mcp supports and presents the format for each type. operands are stored in memory with the least significant digit at the lowest memory address. pro- grams retrieve these values by generating the low- est address. for maximum system performance, all operands should start at physical-memory address- es evenly divisible by four (doubleword boundaries); operands may begin at any other addresses, but will require extra memory cycles to access the entire op- erand. internally, the intel387 dx mcp holds all numbers in the extended-precision real format. instructions that load operands from memory automatically convert operands represented in memory as 16-, 32-, or 64- bit integers, 32- or 64-bit floating-point numbers, or 18-digit packed bcd numbers into extended-preci- sion real format. instructions that store operands in memory perform the inverse type conversion. 2.2 numeric operands a typical mcp instruction accepts one or two oper- ands and produces a single result. in two-operand instructions, one operand is the contents of an mcp register, while the other may be a memory location. the operands of some instructions are predefined; for example fsqrt always takes the square root of the number in the top stack element. 6 6
intel387 tm dx math coprocessor table 2.1. intel387 tm dx mcp data type representation in memory 240448 2 notes: (1) s e sign bit (0 e positive, 1 e negative) (2) d n e decimal digit (two per byte) (3) x e bits have no significance; intel387 tm dx mcp ignores when loading, zeros when storing (4) u e position of implicit binary point (5) i e integer bit of significand; stored in temporary real, implicit in single and double precision (6) exponent bias (normalized values): single: 127 (7fh) double: 1023 (3ffh) extended real: 16383 (3fffh) (7) packed bcd: ( b 1) s (d 17 ...d 0 ) (8) real: ( b 1) s (2 e-bias )(f 0 f 1 ...) 7 7
intel387 tm dx math coprocessor 15 0 tag (7) tag (6) tag (5) tag (4) tag (3) tag (2) tag (1) tag (0) note: the index i of tag(i) is not top-relative. a program typically uses the ``top'' field of status word to determine which tag(i) field refers to logical top of stack. tag values: 00 e valid 01 e zero 10 e qnan, snan, infinity, denormal and unsupported formats 11 e empty figure 2.1. intel387 tm dx mcp tag word 2.3 register set figure 1.1 shows the intel387 dx mcp register set. when an mcp is present in a system, programmers may use these registers in addition to the registers normally available on the intel386 dx cpu. 2.3.1 data registers intel387 dx mcp computations use the mcp's data registers. these eight 80-bit registers provide the equivalent capacity of twenty 32-bit registers. each of the eight data registers in the mcp is 80 bits wide and is divided into ``fields'' corresponding to the mcps extended-precision real data type. the intel387 dx mcp register set can be accessed either as a stack, with instructions operating on the top one or two stack elements, or as a fixed register set, with instructions operating on explicitly designat- ed registers. the top field in the status word identi- fies the current top-of-stack register. a ``push'' oper- ation decrements top by one and loads a value into the new top register. a ``pop'' operation stores the value from the current top register and then incre- ments top by one. like the intel386 dx microproc- essor stacks in memory, the mcp register stack grows ``down'' toward lower-addressed registers. instructions may address the data registers either implicitly or explicitly. many instructions operate on the register at the top of the stack. these instruc- tions implicitly address the register at which top points. other instructions allow the programmer to explicitly specify which register to user. this explicit register addressing is also relative to top. 2.3.2 tag word the tag word marks the content of each numeric data register, as figure 2.1 shows. each two-bit tag represents one of the eight numerics registers. the principal function of the tag word is to optimize the mcps performance and stack handling by making it possible to distinguish between empty and nonemp- ty register locations. it also enables exception han- dlers to check the contents of a stack location with- out the need to perform complex decoding of the actual data. 8 8
intel387 tm dx math coprocessor 240448 3 es is set if any unmasked exception bit is set; cleared otherwise. see table 2.2 for interpretation of condition code. top values: 000 e register 0 is top of stack 001 e register 1 is top of stack # # # 111 e register 7 is top of stack for definitions of exceptions, refer to the section entitled ``exception handling'' figure 2.2. mcp status word 2.3.3 status word the 16-bit status word (in the status register) shown in figure 2.2 reflects the overall state of the mcp. it may be read and inspected by cpu code. bit 15, the b-bit (busy bit) is included for 8087 com- patibility only. it reflects the contents of the es bit (bit 7 of the status word), not the status of the busy y output of the intel387 dx mcp. bits 13 11 (top) point to the intel387 dx mcp reg- ister that is the current top-of-stack. the four numeric condition code bits (c 3 c 0 ) are similar to the flags in a cpu; instructions that per- form arithmetic operations update these bits to re- flect the outcome. the effects of these instructions on the condition code are summarized in tables 2.2 through 2.5. bit 7 is the error summary (es) status bit. this bit is set if any unmasked exception bit is set; it is clear otherwise. if this bit is set, the error y signal is asserted. bit 6 is the stack flag (sf). this bit is used to distin- guish invalid operations due to stack overflow or un- derflow from other kinds of invalid operations. when sf is set, bit 9 (c 1 ) distinguishes between stack overflow (c 1 e 1) and underflow (c 1 e 0). figure 2.2 shows the six exception flags in bits 5 0 of the status word. bits 5 0 are set to indicate that the mcp has detected an exception while executing an instruction. a later section entitled ``exception handling'' explains how they are set and used. note that when a new value is loaded into the status word by the fldenv or frstor instruction, the value of es (bit 7) and its reflection in the b-bit (bit 15) are not derived from the values loaded from memory but rather are dependent upon the values of the exception flags (bits 5 0) in the status word and their corresponding masks in the control word. if es is set in such a case, the error y output of the mcp is activated immediately. 9 9
intel387 tm dx math coprocessor table 2.2. condition code interpretation instruction c0 (s) c3 (z) c1 (a) c2 (c) fprem, fprem1 three least significant bits reduction (see table 2.3) of quotient 0 e complete q2 q0 q1 1 e incomplete or o/u y fcom, fcomp, fcompp, ftst, result of comparison zero operand is not fucom, fucomp, (see table 2.4) or o/u y comparable fucompp, ficom, (table 2.4) ficomp fxam operand class sign operand class (see table 2.5) or o/u y (table 2.5) fchs, fabs, fxch, fincstp, fdecstp, zero constant loads, undefined undefined fxtract, fld, or o/u y fild, fbld, fstp (ext real) fist, fbstp, frndint, fst, fstp, fadd, fmul, roundup fdiv, fdivr, undefined undefined fsub, fsubr, or o/u y fscale, fsqrt, fpatan, f2xm1, fyl2x, fyl2xp1 fptan, fsin roundup reduction fcos, fsincos undefined or o/u y ,0 e complete undefined 1 e incomplete if c2 e 1 fldenv, frstor each bit loaded from memory fldcw, fstenv, fstcw, fstsw, undefined fclex, finit, fsave o/u y when both ie and sf bits of status word are set, indicating a stack exception, this bit distinguishes between stack overflow (c1 e 1) and underflow (c1 e 0). reduction if fprem or fprem1 produces a remainder that is less than the modulus, reduction is complete. when reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to further reduction. for fptan, fsin, fcos, and fsincos, the reduction bit is set if the operand at the top of the stack is too large. in this case the original operand remains at the top of the stack. roundup when the pe bit of the status word is set, this bit indicates whether the last rounding in the instruction was upward. undefined do not rely on finding any specific value in these bits. 10 10
intel387 tm dx math coprocessor table 2.3. condition code interpretation after fprem and fprem1 instructions condition code interpretation after fprem and fprem1 c2 c3 c1 c0 incomplete reduction: 1 x x x further interation required for complete reduction q1 q0 q2 q mod8 000 0 010 1 complete reduction: 0 100 2 c0, c3, c1 contain three least 110 3 significant bits of quotient 001 4 011 5 101 6 111 7 table 2.4. condition code resulting from comparison order c3 c2 c0 top l operand 0 0 0 top k operand 0 0 1 top e operand 1 0 0 unordered 1 1 1 table 2.5. condition code defining operand class c3 c2 c1 c0 value at top 0000 a unsupported 0001 a nan 0010 b unsupported 0011 b nan 0100 a normal 0101 a infinity 0110 b normal 0111 b infinity 1000 a 0 1001 a empty 1010 b 0 1011 b empty 1100 a denormal 1110 b denormal 11 11
intel387 tm dx math coprocessor 2.3.4 instruction and data pointers because the mcp operates in parallel with the cpu, any errors detected by the mcp may be reported after the cpu has executed the esc instruction which caused it. to allow identification of the failing numeric instruction, the intel386 dx microprocessor and intel387 dx math coprocessor contains two pointer registers that supply the address of the fail- ing numeric instruction and the address of its numer- ic memory operand (if appropriate). the instruction and data pointers are provided for user-written error handlers. these registers are ac- tually located in the intel386 dx cpu, but appear to be located in the mcp because they are accessed by the esc instructions fldenv, fstenv, fsave, and frstor. (in the 8086/8087 and 80286/80287, these registers are located in the mcp.) whenever the intel386 dx cpu decodes a new esc instruc- tion, it saves the address of the instruction (including any prefixes that may be present), the address of the operand (if present), and the opcode. the instruction and data pointers appear in one of four formats depending on the operating mode of the intel386 dx microprocessor (protected mode or real-address mode) and depending on the operand- size attribute in effect (32-bit operand or 16-bit oper- and). when the intel386 dx microprocessor is in vir- tual-8086 mode, the real-address mode formats are used. (see figures 2.3 through 2.6.) the esc in- structions fldenv, fstenv, fsave, and frstor are used to transfer these values between the in- tel386 dx microprocessor registers and memory. note that the value of the data pointer is undefined if the prior esc instruction did not have a memory op- erand. 32-bit protected mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 ip offset c 00000 opcode 10..0 cs selector 10 data operand offset 14 reserved operand selector 18 figure 2.3. protected mode intel387 tm dx mcp instruction and data pointer image in memory, 32-bit format 12 12
intel387 tm dx math coprocessor 32-bit real-address mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 reserved instruction pointer 15..0 c 0000 instruction pointer 31..16 0 opcode 10..0 10 reserved operand pointer 15..0 14 0000 operand pointer 31..16 0000 00000000 18 figure 2.4. real mode intel387 tm dx mcp instruction and data pointer image in memory, 32-bit format 16-bit protected mode format 15 7 0 control word 0 status word 2 tag word 4 ip offset 6 cs selector 8 operand offset a operand selector c figure 2.5. protected mode intel387 tm dx mcp instruction and data pointer image in memory, 16-bit format 16-bit real-address mode and virtual-8086 mode format 15 7 0 control word 0 status word 2 tag word 4 instruction pointer 15..0 6 ip19.16 0 opcode 10..0 8 operand pointer 15..0 a dp 19.16 00000000000 0 c figure 2.6. real mode intel387 tm dx mcp instruction and data pointer image in memory, 16-bit format 13 13
intel387 tm dx math coprocessor 240448 4 precision control rounding control 00e24 bits (single precision) 00eround to nearest or even 01e(reserved) 01eround down (toward b % ) 10e53 bits (double precision) 10eround up (toward a % ) 11e64 bits (extended precision) 11echop (truncate toward zero) figure 2.7. intel387 tm dx mcp control word 2.3.5 control word the mcp provides several processing options that are selected by loading a control word from memory into the control register. figure 2.7 shows the format and encoding of fields in the control word. the low-order byte of this control word configures the mcp error and exception masking. bits 5 0 of the control word contain individual masks for each of the six exceptions that the mcp recognizes. the high-order byte of the control word configures the mcp operating mode, including precision and rounding. # bit 12 no longer defines infinity control and is a reserved bit. only affine closure is supported for infinity arithmetic. the bit is initialized to zero after reset or finit and is changeable upon loading the cw. programs must ignore this bit. # the rounding control (rc) bits (bits 11 10) pro- vide for directed rounding and true chop, as well as the unbiased round to nearest even mode specified in the ieee standard. rounding control affects only those instructions that perform rounding at the end of the operation (and thus can generate a precision exception); namely, fst, fstp, fist, all arithmetic instructions (ex- cept fprem, fprem1, fxtract, fabs, and fchs), and all transcendental instructions. # the precision control (pc) bits (bits 9 8) can be used to set the mcp internal operating precision of the significand at less than the default of 64 bits (extended precision). this can be useful in providing compatibility with early generation arith- metic processors of smaller precision. pc affects only the instructions add, sub, div, mul, and sqrt. for all other instructions, either the preci- sion is determined by the opcode or extended precision is used. 2.4 interrupt description several interrupts of the intel386 dx cpu are used to report exceptional conditions while executing nu- meric programs in either real or protected mode. ta- ble 2.6 shows these interrupts and their causes. 14 14
intel387 tm dx math coprocessor table 2.6. intel386 tm dx microprocessor interrupt vectors reserved for mcp interrupt cause of interrupt number 7 an esc instruction was encountered when em or ts of the intel386 tm dx cpu control register zero (cr0) was set. em e 1 indicates that software emulation of the instruction is required. when ts is set, either an esc or wait instruction causes interrupt 7. this indicates that the current mcp context may not belong to the current task. 9 an operand of a coprocessor instruction wrapped around an addressing limit (0ffffh for small segments, 0ffffffffh for big segments, zero for expand-down segments) and spanned inaccessible addresses (1) . the failing numerics instruction is not restartable. the address of the failing numerics instruction and data operand may be lost; an fstenv does not return reliable addresses. as with the 80286/80287, the segment overrun exception should be handled by executing an fninit instruction (i.e. an finit without a preceding wait). the return address on the stack does not necessarily point to the failing instruction nor to the following instruction. the interrupt can be avoided by never allowing numeric data to start within 108 bytes of the end of a segment. 13 the first word or doubleword of a numeric operand is not entirely within the limit of its segment. the return address pushed onto the stack of the exception handler points at the esc instruction that caused the exception, including any prefixes. the intel387 tm dx mcp has not executed this instruction; the instruction pointer and data pointer register refer to a previous, correctly executed instruction. 16 the previous numerics instruction caused an unmasked exception. the address of the faulty instruction and the address of its operand are stored in the instruction pointer and data pointer registers. only esc and wait instructions can cause this interrupt. the intel386 tm dx cpu return address pushed onto the stack of the exception handler points to a wait or esc instruction (including prefixes). this instruction can be restarted after clearing the exception condition in the mcp. fninit, fnclex, fnstsw, fnstenv, and fnsave cannot cause this interrupt. 1. an operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid address in the segment. because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the segment. there are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing limit (e.g. addressing limit is ffffh and segment limit is fffdh) the operand will span addresses that are not within the segment (e.g. an 8-byte operand that starts at valid offset fffc will span addresses fffc ffff and 0000-0003; however addresses fffe and ffff are not valid, because they exceed the limit); 2) if the operand begins and ends in present and accessible pages but intermediate bytes of the operand fall in a not-present page or a page to which the procedure does not have access rights. 2.5 exception handling the intel387 dx mcp detects six different exception conditions that can occur during instruction execu- tion. table 2.7 lists the exception conditions in order of precedence, showing for each the cause and the default action taken by the mcp if the exception is masked by its corresponding mask bit in the control word. any exception that is not masked by the control word sets the corresponding exception flag of the status word, sets the es bit of the status word, and asserts the error y signal. when the cpu at- tempts to execute another esc instruction or wait, exception 7 occurs. the exception condition must be resolved via an interrupt service routine. the in- tel386 dx microprocessor saves the address of the floating-point instruction that caused the excep- tion and the address of any memory operand re- quired by that instruction. 2.6 initialization intel387 dx mcp initialization software must exe- cute an fninit instruction (i.e. an finit without a preceding wait) to clear error y . after a hardware reset, the error y output is asserted to indicate that a intel387 dx mcp is present. to accomplish this, the ie and es bits of the status word are set, and the im bit in the control word is reset. after fninit, the status word and the control word have the same values as in an 80287 after reset. 15 15
intel387 tm dx math coprocessor 2.7 8087 and 80287 compatibility this section summarizes the differences between the intel387 dx mcp and the 80287. any migration from the 8087 directly to the intel387 dx mcp must also take into account the differences between the 8087 and the 80287 as listed in appendix a. many changes have been designed into the intel387 dx mcp to directly support the ieee standard in hardware. these changes result in increased per- formance by eliminating the need for software that supports the standard. 2.7.1 general differences the intel387 dx mcp supports only affine closure for infinity arithmetic, not projective closure. bit 12 of the control word (cw) no longer defines infinity control. it is a reserved bit; but it is initialized to zero after reset or finit and is changeable upon load- ing the cw. programs must ignore this bit. operands for fscale and fpatan are no longer restricted in range (except for g % ); f2xm1 and fptan accept a wider range of operands. the results of transcendental operations may be slightly different from those computed by 80287. in the case of fptan, the intel387 dx mcp supplies a true tangent result in st(1), and (always) a floating point 1 in st. rounding control is in effect for fld constant . software cannot change entries of the tag word to values (other than empty) that do not reflect the ac- tual register contents. after reset, finit, and incomplete fprem, the in- tel387 dx mcp resets to zero the condition code bits c 3 c 0 of the status word. in conformance with the ieee standard, the intel387 dx mcp does not support the special data formats: pseudozero, pseudo-nan, pseudoinfinity, and un- normal. table 2.7. exceptions exception cause default action (if exception is masked) invalid operation on a signaling nan, unsupported format, result is a quiet nan, integer operation indeterminate form (0 * % , 0/0, ( a % ) a ( b % ), etc.), or indefinite, or bcd indefinite stack overflow/underflow (sf is also set). denormalized at least one of the operands is denormalized, i.e. it has normal processing operand the smallest exponent but a nonzero significand. continues zero divisor the divisor is zero while the dividend is a noninfinite, result is % nonzero number. overflow the result is too large in magnitude to fit in the specified result is largest finite value format. or % underflow the true result is nonzero but too small to be result is denormalized or represented in the specified format, and, if underflow zero exception is masked, denormalization causes loss of accuracy. inexact the true result is not exactly representable in the normal processing result specified format (e.g. 1/3); the result is rounded continues (precision) according to the rounding mode. 16 16
intel387 tm dx math coprocessor 2.7.2 exceptions a number of differences exist due to changes in the ieee standard and to functional improvements to the architecture of the intel387 dx mcp: 1. when the overflow or underflow exception is masked, the intel387 dx mcp differs from the 80287 in rounding when overflow or underflow occurs. the intel387 dx mcp produces results that are consistent with the rounding mode. 2. when the underflow exception is masked, the intel387 dx mcp sets its underflow flag only if there is also a loss of accuracy during denormali- zation. 3. fewer invalid-operation exceptions due to de- normal operands, because the instructions fsqrt, fdiv, fprem, and conversions to bcd or to integer normalize denormal operands be- fore proceeding. 4. the fsqrt, fbstp, and fprem instructions may cause underflow, because they support de- normal operands. 5. the denormal exception can occur during the transcendental instructions and the fxtract instruction. 6. the denormal exception no longer takes prece- dence over all other exceptions. 7. when the denormal exception is masked, the in- tel387 dx mcp automatically normalizes denor- mal operands. the 8087/80287 performs unnor- mal arithmetic, which might produce an unnor- mal result. 8. when the operand is zero, the fxtract in- struction reports a zero-divide exception and leaves b % in st(1). 9. the status word has a new bit (sf) that signals when invalid-operation exceptions are due to stack underflow or overflow. 10. fld extended precision no longer reports denor- mal exceptions, because the instruction is not numeric. 11. fld single/double precision when the operand is denormal converts the number to extended precision and signals the denormalized operand exception. when loading a signaling nan, fld single/double precision signals an invalid-oper- and exception. 12. the intel387 dx mcp only generates quiet nans (as on the 80287); however, the intel387 dx mcp distinguishes between quiet nans and signaling nans. signaling nans trigger excep- tions when they are used as operands; quiet nans do not (except for fcom, fist, and fbstp which also raise ie for quiet nans). 13. when stack overflow occurs during fptan and overflow is masked, both st(0) and st(1) con- tain quiet nans. the 80287/8087 leaves the original operand in st(1) intact. 14. when the scaling factor is g % , the fscale (st(0), st(1)) instruction behaves as follows (st(0) and st(1) contain the scaled and scaling operands respectively): # fscale(0, % ) generates the invalid operation exception. # fscale(finite, b % ) generates zero with the same sign as the scaled operand. # fscale(finite, a % ) generates % with the same sign as the scaled operand. the 8087/80287 returns zero in the first case and raises the invalid-operation exception in the other cases. 15. the intel387 dx mcp returns signed infinity/ zero as the unmasked response to massive overflow/underflow. the 8087 and 80287 sup- port a limited range for the scaling factor; within this range either massive overflow/underflow do not occur or undefined results are produced. 3.0 hardware interface in the following description of hardware interface, the y symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage. when no y is present after the signal name, the signal is asserted when at the high voltage level. 3.1 signal description in the following signal descriptions, the intel387 dx math coprocessor pins are grouped by function as follows: 1. execution controlecpuclk2, numclk2, ckm, resetin 2. mcp handshakeepereq, busy y , error y 3. bus interface pinsed31 d0, w/r y , ads y , ready y , readyo y 4. chip/port selectesten, nps1 y , nps2, cmd0 y 5. power suppliesev cc ,v ss table 3.1 lists every pin by its identifier, gives a brief description of its function, and lists some of its char- acteristics. all output signals are tristate; they leave floating state only when sten is active. the output buffers of the bidirectional data pins d31 d0 are also tristate; they leave floating state only in read cycles when the mcp is selected (i.e. when sten, nps1 y , and nps2 are all active). figure 3.1 and table 3.2 together show the location of every pin in the pin grid array. 17 17
intel387 tm dx math coprocessor table 3.1. intel387 tm dx mcp pin summary pin function active input/ referenced name state output to cpuclk2 intel386 tm dx cpu clock 2 i numclk2 intel387 tm dx mcp clock 2 i ckm intel387 tm dx mcp clocking mode i resetin system reset high i cpuclk2 pereq processor extension high o cpuclk2/sten request busy y busy status low o cpuclk2/sten error y error status low o numclk2/sten d31 d0 data pins high i/o cpuclk2 w/r y write/read bus cycle hi/lo i cpuclk2 ads y address strobe low i cpuclk2 ready y bus ready input low i cpuclk2 readyo y ready output low o cpuclk2/sten sten status enable high i cpuclk2 nps1 y mcp select y 1 low i cpuclk2 nps2 mcp select y 2 high i cpuclk2 cmd0 y command low i cpuclk2 v cc i v ss i note: sten is referenced to only when getting the output pins into or out of tristate mode. table 3.2. intel387 tm dx mcp pin cross-reference ads y ek7 busy y ek2 ckm e j11 cpuclk24 e k10 cmd0 y el8 d0 e h2 d1 e h1 d2 e g2 d3 e g1 d4 e d2 d5 e d1 d6 e c2 d7 e c1 d8 e b1 d9 e a2 d10 e b3 d11 e a3 d12 e a4 d13 e b5 d14 e a5 d15 e b6 d16 e a7 d17 e b8 d18 e a8 d19 e b9 d20 e b10 d21 e a10 d22 e b11 d23 e c10 d24 e d10 d25 e d11 d26 e e10 d27 e e11 d28 e g10 d29 e g11 d30 e h10 d31 e h11 error y el2 nps1 y el6 nps2 e k6 numclk2 e k11 pereq e k1 ready y ek8 readyo y el3 resetin e l10 sten e l4 w/r y ek4 v cc e a6, a9, b4, e1, f1, f10, j2, k5, l7 v ss e b2, b7, c11, e2, f2, f11, j1, j10, l5 no connect e k9 tie high e k3, l9 * * tie high pins may either be tied high with a pullup resistor or connected to v cc . 18 18
intel387 tm dx math coprocessor 240448 5 * pin 1 240448 6 * pin 1 figure 3.1. intel387 tm dx mcp pin configuration 19 19
intel387 tm dx math coprocessor 3.1.1 intel386 tm dx cpu clock 2 (cpuclk2) this input uses the intel386 dx cpu clk2 signal to time the bus control logic. several other mcp sig- nals are referenced to the rising edge of this signal. when ckm e 1 (synchronous mode) this pin also clocks the data interface and control unit and the floating-point unit of the mcp. this pin requires mos-level input. the signal on this pin is divided by two to produce the internal clock signal clk. 3.1.2 intel387 tm dx mcp clock 2 (numclk2) when ckm e 0 (asynchronous mode) this pin pro- vides the clock for the data interface and control unit and the floating-point unit of the mcp. in this case, the ratio of the frequency of numclk2 to the fre- quency of cpuclk2 must lie within the range 10:16 to 14:10. when ckm e 1 (synchronous mode) this pin is ignored; cpuclk2 is used instead for the data interface and control unit and the floating-point unit. this pin requires ttl-level input. 3.1.3 intel387 tm dx mcp clocking mode (ckm) this pin is a strapping option. when it is strapped to v cc , the mcp operates in synchronous mode; when strapped to v ss , the mcp operates in asynchronous mode. these modes relate to clocking of the data interface and control unit and the floating-point unit only; the bus control logic always operates synchro- nously with respect to the intel386 dx microproces- sor. 240448 7 figure 3.2. asynchronous operation 20 20
intel387 tm dx math coprocessor 3.1.4 system reset (resetin) a low to high transition on this pin causes the mcp to terminate its present activity and to enter a dormant state. resetin must remain high for at least 40 numclk2 periods. the high to low tran- sitions of resetin must be synchronous with cpuclk2, so that the phase of the internal clock of the bus control logic (which is the cpuclk2 divided by 2) is the same as the phase of the internal clock of the intel386 dx cpu. after resetin goes low, at least 50 numclk2 periods must pass before the first mcp instruction is written into the intel387 dx mcp. this pin should be connected to the intel386 dx cpu reset pin. table 3.3 shows the status of other pins after a reset. table 3.3. output pin status during reset pin value pin name high readyo y , busy y low pereq, error y tri-state off d31 d0 3.1.5 processor extension request (pereq) when active, this pin signals to the intel386 dx cpu that the mcp is ready for data transfer to/from its data fifo. when all data is written to or read from the data fifo, pereq is deactivated. this signal always goes inactive before busy y goes inactive. this signal is referenced to cpuclk2. it should be connected to the intel386 dx cpu pereq input. 3.1.6 busy status (busy y ) when active, this pin signals to the intel386 dx cpu that the mcp is currently executing an instruction. this signal is referenced to cpuclk2. it should be connected to the intel386 dx cpu busy y pin. 3.1.7 error status (error y ) this pin reflects the es bits of the status register. when active, it indicates that an unmasked excep- tion has occurred (except that, immediately after a reset, it indicates to the intel386 dx microprocessor that a intel387 dx mcp is present in the system). this signal can be changed to inactive state only by the following instructions (without a preceding wait): fninit, fnclex, fnstenv, and fnsave. this signal is referenced to numclk2. it should be connected to the intel386 dx cpu error y pin. 3.1.8 data pins (d31 d0) these bidirectional pins are used to transfer data and opcodes between the intel386 dx cpu and in- tel387 dx mcp. they are normally connected direct- ly to the corresponding intel386 dx cpu data pins. high state indicates a value of one. d0 is the least significant data bit. timings are referenced to cpuclk2. 3.1.9 write/read bus cycle (w/r y ) this signal indicates to the mcp whether the in- tel386 dx cpu bus cycle in progress is a read or a write cycle. this pin should be connected directly to the intel386 dx cpu w/r y pin. high indicates a write cycle; low, a read cycle. this input is ignored if any of the signals sten, nps1 y , or nps2 is inac- tive. setup and hold times are referenced to cpuclk2. 3.1.10 address strobe (ads y ) this input, in conjunction with the ready y input indicates when the mcp bus-control logic may sam- ple w/r y and the chip-select signals. setup and hold times are referenced to cpuclk2. this pin should be connected to the intel386 dx cpu ads y pin. 21 21
intel387 tm dx math coprocessor 3.1.11 bus ready input (ready y ) this input indicates to the mcp when a intel386 dx cpu bus cycle is to be terminated. it is used by the bus-control logic to trace bus activities. bus cycles can be extended indefinitely until terminated by ready y . this input should be connected to the same signal that drives the intel386 dx cpu ready y input. setup and hold times are refer- enced to cpuclk2. 3.1.12 ready output (readyo y ) this pin is activated at such a time that write cycles are terminated after two clocks (except fldenv and frstor) and read cycles after three clocks. in configurations where no extra wait states are re- quired, this pin must directly or indirectly drive the intel386 dx cpu ready y input. refer to section 3.4 ``bus operation'' for details. this pin is activated only during bus cycles that select the mcp. this sig- nal is referenced to cpuclk2. 3.1.13 status enable (sten) this pin serves as a chip select for the mcp. when inactive, this pin forces busy y , pereq, error y , and readyo y outputs into floating state. d31 d0 are normally floating and leave floating state only if sten is active and additional conditions are met. sten also causes the chip to recognize its other chip-select inputs. sten makes it easier to do on- board testing (using the overdrive method) of other chips in systems containing the mcp. sten should be pulled up with a resistor so that it can be pulled down when testing. in boards that do not use on- board testing, sten should be connected to v cc . setup and hold times are relative to cpuclk2. note that sten must maintain the same setup and hold times as nps1 y , nps2, and cmd0 y (i.e. if sten changes state during a intel387 dx mcp bus cycle, it should change state during the same clk period as the nps1 y , nps2, and cmd0 y signals). 3.1.14 mcp select y 1 (nps1 y ) when active (along with sten and nps2) in the first period of a intel386 dx cpu bus cycle, this signal indicates that the purpose of the bus cycle is to com- municate with the mcp. this pin should be connect- ed directly to the intel386 dx cpu m/io y pin, so that the mcp is selected only when the intel386 dx cpu performs i/o cycles. setup and hold times are referenced to cpuclk2. 3.1.15 mcp select y 2 (nps2) when active (along with sten and nps1 y )inthe first period of an intel386 dx cpu bus cycle, this signal indicates that the purpose of the bus cycle is to communicate with the mcp. this pin should be connected directly to the intel386 dx cpu a31 pin, so that the mcp is selected only when the intel386 dx cpu uses one of the i/o addresses reserved for the mcp (800000f8 or 800000fc). setup and hold times are referenced to cpuclk2. 3.1.16 command (cmd0 y ) during a write cycle, this signal indicates whether an opcode (cmd0 y active) or data (cmd0 y inactive) is being sent to the mcp. during a read cycle, it indicates whether the control or status register (cmd0 y active) or a data register (cmd0 y inactive) is being read. cmd0 y should be connected directly to the a2 output of the intel386 dx microprocessor. setup and hold times are referenced to cpuclk2. 3.2 processor architecture as shown by the block diagram on the front page, the mcp is internally divided into three sections: the bus control logic (bcl), the data interface and con- trol unit, and the floating point unit (fpu). the fpu (with the support of the control unit which contains the sequencer and other support units) executes all numerics instructions. the data interface and control unit is responsible for the data flow to and from the fpu and the control registers, for receiving the in- structions, decoding them, and sequencing the mi- croinstructions, and for handling some of the admin- istrative instructions. the bcl is responsible for the intel386 dx cpu bus tracking and interface. the bcl is the only unit in the intel387 dx mcp that must run synchronously with the intel386 dx cpu; the rest of the mcp can run asynchronously with respect to the intel386 dx microprocessor. 22 22
intel387 tm dx math coprocessor 3.2.1 bus control logic the bcl communicates solely with the cpu using i/o bus cycles. the bcl appears to the cpu as a special peripheral device. it is special in two re- spects: the cpu initiates i/o automatically when it encounters esc instructions, and the cpu uses re- served i/o addresses to communicate with the bcl. the bcl does not communicate directly with memo- ry. the cpu performs all memory access, transfer- ring input operands from memory to the mcp and transferring outputs from the mcp to memory. 3.2.2 data interface and control unit the data interface and control unit latches the data and, subject to bcl control, directs the data to the fifo or the instruction decoder. the instruction de- coder decodes the esc instructions sent to it by the cpu and generates controls that direct the data flow in the fifo. it also triggers the microinstruction se- quencer that controls execution of each instruction. if the esc instruction is finit, fclex, fstsw, fstsw ax, or fstcw, the control executes it inde- pendently of the fpu and the sequencer. the data interface and control unit is the one that generates the busy y , pereq and error y signals that syn- chronize intel387 dx mcp activities with the in- tel386 dx cpu. it also supports the fpu in all opera- tions that it cannot perform alone (e.g. exceptions handling, transcendental operations, etc.). 3.2.3 floating point unit the fpu executes all instructions that involve the register stack, including arithmetic, logical, transcen- dental, constant, and data transfer instructions. the data path in the fpu is 84 bits wide (68 significant bits, 15 exponent bits, and a sign bit) which allows internal operand transfers to be performed at very high speeds. 3.3 system configuration as an extension to the intel386 dx microprocessor, the intel387 dx math coprocessor can be connect- ed to the cpu as shown by figure 3.3. a dedicated 240448 8 figure 3.3. intel386 tm dx microprocessor and intel387 tm dx math coprocessor system configuration 23 23
intel387 tm dx math coprocessor table 3.4. bus cycles definition sten nps1 y nps2 cmd0 y w/r y bus cycle type 0 x x x x mcp not selected and all outputs in floating state 1 1 x x x mcp not selected 1 x 0 x x mcp not selected 1 0 1 0 0 cw or sw read from mcp 1 0 1 0 1 opcode write to mcp 1 0 1 1 0 data read from mcp 1 0 1 1 1 data write to mcp communication protocol makes possible high-speed transfer of opcodes and operands between the in- tel386 dx cpu and intel387 dx mcp. the intel387 dx mcp is designed so that no additional compo- nents are required for interface with the intel386 dx cpu. the intel387 dx mcp shares the 32-bit wide local bus of the intel386 dx cpu and most control pins of the intel387 dx mcp are connected directly to pins of the intel386 dx microprocessor. 3.3.1 bus cycle tracking the ads y and ready y signals allow the mcp to track the beginning and end of the intel386 dx cpu bus cycles, respectively. when ads y is asserted at the same time as the mcp chip-select inputs, the bus cycle is intended for the mcp. to signal the end of a bus cycle for the mcp, ready y may be assert- ed directly or indirectly by the mcp or by other bus- control logic. refer to table 3.4 for definition of the types of mcp bus cycles. 3.3.2 mcp addressing the nps1 y , nps2 and sten signals allow the mcp to identify which bus cycles are intended for the mcp. the mcp responds only to i/o cycles when bit 31 of the i/o address is set. in other words, the mcp acts as an i/o device in a reserved i/o address space. because a 31 is used to select the mcp for data transfers, it is not possible for a program running on the intel386 dx cpu to address the mcp with an i/ o instruction. only esc instructions cause the in- tel386 dx microprocessor to communicate with the mcp. the intel386 dx cpu bs16 y input must be inactive during i/o cycles when a 31 is active. 3.3.3 function select the cmd0 y and w/r y signals identify the four kinds of bus cycle: control or status register read, data read, opcode write, data write. 3.3.4 cpu/mcp synchronization the pin pairs busy y , pereq, and error y are used for various aspects of synchronization between the cpu and the mcp. busy y is used to synchronize instruction transfer from the intel386 dx cpu to the mcp. when the mcp recognizes an esc instruction, it asserts busy y . for most esc instructions, the intel386 dx cpu waits for the mcp to deassert busy y before sending the new opcode. the mcp uses the pereq pin of the intel386 dx cpu to signal that the mcp is ready for data transfer to or from its data fifo. the mcp does not directly access memory; rather, the intel386 dx microproc- essor provides memory access services for the mcp. thus, memory access on behalf of the mcp always obeys the rules applicable to the mode of the intel386 dx cpu, whether the intel386 dx cpu be in real-address mode or protected mode. once the intel386 dx cpu initiates an mcp instruc- tion that has operands, the intel386 dx cpu waits for pereq signals that indicate when the mcp is ready for operand transfer. once all operands have been transferred (or if the instruction has no oper- ands) the intel386 dx cpu continues program exe- cution while the mcp executes the esc instruction. in 8086/8087 systems, wait instructions may be required to achieve synchronization of both com- mands and operands. in 80286/80287, intel386 dx microprocessor and intel387 dx math coprocessor systems, wait instructions are required only for op- erand synchronization; namely, after mcp stores to memory (except fstsw and fstcw) or loads from memory. used this way, wait ensures that the val- ue has already been written or read by the mcp be- fore the cpu reads or changes the value. 24 24
intel387 tm dx math coprocessor once it has started to execute a numerics instruction and has transferred the operands from the intel386 dx cpu, the mcp can process the instruction in par- allel with and independent of the host cpu. when the mcp detects an exception, it asserts the er- ror y signal, which causes a intel386 dx cpu in- terrupt. 3.3.5 synchronous or asynchronous modes the internal logic of the intel387 dx mcp (the fpu) can either operate directly from the cpu clock (syn- chronous mode) or from a separate clock (asynchro- nous mode). the two configurations are distin- guished by the ckm pin. in either case, the bus con- trol logic (bcl) of the mcp is synchronized with the cpu clock. use of asynchronous mode allows the intel386 dx cpu and the fpu section of the mcp to run at different speeds. in this case, the ratio of the frequency of numclk2 to the frequency of cpuclk2 must lie within the range 10:16 to 14:10. use of synchronous mode eliminates one clock gen- erator from the board design. 3.3.6 automatic bus cycle termination in configurations where no extra wait states are re- quired, readyo y can be used to drive the intel386 dx cpu ready y input. if this pin is used, it should be connected to the logic that ors all ready out- puts from peripherals on the intel386 dx cpu bus. readyo y is asserted by the mcp only during i/o cycles that select the mcp. refer to section 3.4 ``bus operation'' for details. 3.4 bus operation with respect to the bus interface, the intel387 dx mcp is fully synchronous with the intel386 dx mi- croprocessor. both operate at the same rate, be- cause each generates its internal clk signal by di- viding cpuclk2 by two. the intel386 dx cpu initiates a new bus cycle by activating ads y . the mcp recognizes a bus cycle, if, during the cycle in which ads y is activated, sten, nps1 y , and nps2 are all activated. proper operation is achieved if nps1 y is connected to the m/io y output of the intel386 dx cpu, and nps2 to the a31 output. the intel386 dx cpu's a31 output is guaranteed to be inactive in all bus cycles that do not address the mcp (i.e. i/o cycles to other devic- es, interrupt acknowledge, and reserved types of bus cycles). system logic must not signal a 16-bit bus cycle via the intel386 dx cpu bs16 y input dur- ing i/o cycles when a31 is active. during the clk period in which ads y is activated, the mcp also examines the w/r y input signal to determine whether the cycle is a read or a write cy- cle and examines the cmd0 y input to determine whether an opcode, operand, or control/status reg- ister transfer is to occur. the intel387 dx mcp supports both pipelined and nonpipelined bus cycles. a nonpipelined cycle is one for which the intel386 dx cpu asserts ads y when no other mcp bus cycle is in progress. a pipelined bus cycle is one for which the intel386 dx cpu as- serts ads y and provides valid next-address and control signals as soon as in the second clk period after the ads y assertion for the previous intel386 dx cpu bus cycle. pipelining increases the availabil- ity of the bus by at least one clk period. the mcp supports pipelined bus cycles in order to optimize address pipelining by the intel386 dx cpu for mem- ory cycles. bus operation is described in terms of an abstract state machine . figure 3.4 illustrates the states and state transitions for mcp bus cycles: # t i is the idle state. this is the state of the bus logic after reset, the state to which bus logic returns after evey nonpipelined bus cycle, and the state to which bus logic returns after a series of pipelined cycles. # t rs is the ready y sensitive state. different types of bus cycle may require a minimum of one or two successive t rs states. the bus logic re- mains in t rs state until ready y is sensed, at which point the bus cycle terminates. any number of wait states may be implemented by delaying ready y , thereby causing additional successive t rs states. # t p is the first state for every pipelined bus cycle. 240448 9 figure 3.4. bus state diagram 25 25
intel387 tm dx math coprocessor the readyo y output of the intel387 dx mcp indi- cates when a bus cycle for the mcp may be termi- nated if no extra wait states are required. for all write cycles (except those for the instructions fldenv and frstor), readyo y is always as- serted in the first t rs state, regardless of the num- ber of wait states. for all read cycles and write cy- cles for fldenv and frstor, readyo y is al- ways asserted in the second t rs state, regardless of the number of wait states. these rules apply to both pipelined and nonpipelined cycles. systems de- signers must use readyo y in one of the following ways: 1. connect it (directly or through logic that ors ready signals from other devices) to the ready y inputs of the intel386 dx cpu and in- tel387 dx mcp. 2. use it as one input to a wait-state generator. the following sections illustrate different types of mcp bus cycles. because different instructions have different amounts of overhead before, between, and after op- erand transfer cycles, it is not possible to represent in a few diagrams all of the combinations of succes- sive operand transfer cycles. the following bus-cy- cle diagrams show memory cycles between mcp operand-transfer cycles. note however that, during the instructions fldenv, fstenv, fsave, and frstor, some consecutive accesses to the mcp do not have intervening memory accesses. for the timing relationship between operand transfer cycles and opcode write or other overhead activities, see figure 3.8. 3.4.1 nonpipelined bus cycles figure 3.5 illustrates bus activity for consecutive nonpipelined bus cycles. 3.4.1.1 write cycle at the second clock of the bus cycle, the intel387 dx mcp enters the t rs (ready y -sensitive) state. during this state, the intel387 dx mcp samples the ready y input and stays in this state as long as ready y is inactive. in write cycles, the mcp drives the readyo y sig- nal for one clk period beginning with the second clk of the bus cycle; therefore, the fastest write cycle takes two clk cycles (see cycle 2 of figure 3.5). for the instructions fldenv and frstor, however, the mcp forces a wait state by delaying the activation of readyo y to the second t rs cy- cle (not shown in figure 3.5). when ready y is asserted the mcp returns to the idle state, in which ads y could be asserted again by the intel386 dx microprocessor for the next cy- cle. 3.4.1.2 read cycle at the second clock of the bus cycle, the mcp en- ters the t rs state. see figure 3.5. in this state, the mcp samples the ready y input and stays in this state as long as ready y is inactive. at the rising edge of clk in the second clock period of the cycle, the mcp starts to drive the d31 d0 outputs and continues to drive them as long as it stays in t rs state. in read cycles that address the mcp, at least one wait state must be inserted to insure that the in- tel386 dx cpu latches the correct data. since the mcp starts driving the system data bus only at the rising edge of clk in the second clock period of the bus cycle, not enough time is left for the data signals to propagate and be latched by the intel386 dx cpu at the falling edge of the same clock period. the mcp drives the readyo y signal for one clk peri- od in the third clk of the bus cycle. therefore, if the readyo y output is used to drive the intel386 dx cpu ready y input, one wait state is inserted auto- matically. because one wait state is required for mcp reads, the minimum is three clk cycles per read, as cycle 3 of figure 3.5 shows. when ready y is asserted the mcp returns to the idle state, in which ads y could be asserted again by the intel386 dx cpu for the next cycle. the tran- sition from t rs state to idle state causes the mcp to put the tristate d31 d0 outputs into the floating state, allowing another device to drive the system data bus. 26 26
intel387 tm dx math coprocessor 240448 10 cycle s1&2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads. cycle s3&4 represent part of the operand transfer cycle for a store operation. * cycle s1&2 could repeat here or t i states for various non-operand transfer cycles and overhead. figure 3.5. nonpipelined read and write cycles 3.4.2 pipelined bus cycles because all the activities of the intel387 dx mcp bus interface occur either during the t rs state or during the transitions to or from that state, the only difference between a pipelined and a nonpipelined cycle is the manner of changing from one state to another. the exact activities in each state are de- tailed in the previous section ``nonpipelined bus cy- cles''. when the intel386 dx cpu asserts ads y before the end of a bus cycle, both ads y and ready y are active during a t rs state. this condition causes the mcp to change to a different state named t p . the mcp activities in the transition from a t rs state to a t p state are exactly the same as those in the transition from a t rs state to a t i state in nonpipe- lined cycles. t p state is metastable; therefore, one clock period later the mcp returns to t rs state. in consecutive pipelined cycles, the mcp bus logic uses only t rs and t p states. figure 3.6 shows the fastest transition into and out of the pipelined bus cycles. cycle 1 in this figure represents a nonpipelined cycle. (nonpipelined write cycles with only one t rs state (i.e. no wait states) are always followed by another nonpipelined cycle, because ready y is asserted before the earliest possible assertion of ads y for the next cycle.) figure 3.7 shows the pipelined write and read cycles with one additional t rs states beyond the minimum required. to delay the assertion of ready y re- quires external logic. 27 27
intel387 tm dx math coprocessor 3.4.3 bus cycles of mixed type when the intel387 dx mcp bus logic is in the t rs state, it distinguishes between nonpipelined and pipelined cycles according to the behavior of ads y and ready y . in a nonpipelined cycle, only ready y is activated, and the transition is from t rs to idle state. in a pipelined cycle, both ready y and ads y are active and the transition is first from t rs state to t p state then, after one clock period, back to t rs state. 3.4.4 busy y and pereq timing relationship figure 3.8 shows the activation of busy y at the beginning of instruction execution and its deactiva- tion after execution of the instruction is complete. when possible, the intel387 dx mcp may deacti- vate busy y prior to the completion of the current instruction allowing the cpu to transfer the next in- struction's opcode and operands. pereq is activat- ed in this interval. if error y (not shown in the diagram) is ever asserted, it would occur at least six cpuclk2 periods after the deactivation of pereq and at least six cpuclk2 periods before the deacti- vation of busy y . figure 3.8 shows also that sten is activated at the beginning of a bus cycle. 240448 11 cycle 1 cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total. the opcode write cycles and other overhead are not shown. note that the next cycle will be a pipelined cycle if both ready y and ads y are sampled active at the end of a t rs state of the current cycle. figure 3.6. fastest transitions to and from pipelined cycles 28 28
intel387 tm dx math coprocessor 240448 12 note: 1. cycles between operand write to the mcp and storing result. figure 3.7. pipelined cycles with wait states 240448 13 notes: 1. instruction dependent. 2. pereq is an asynchronous input to the intel386 tm dx microprocessor; it may not be asserted (instruction depen- dent). 3. more operand transfers. 4. memory read (operand) cycle is not shown. figure 3.8. sten, busy y and pereq timing relationship 29 29
intel387 tm dx math coprocessor 4.0 electrical data 4.1 absolute maximum ratings * case temperature t c under bias b 65 cto a 110 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5 to v cc a 0.5v power dissipation1.5w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 4.2 dc characteristics table 4.1. dc specifications t c e 0 to 85 c, v cc e 5v g 5% symbol parameter min max units test conditions v il input lo voltage b 0.3 a 0.8 v (note 1) v ih input hi voltage 2.0 v cc a 0.3 v (note 1) v cl cpuclk2 input lo voltage b 0.3 a 0.8 v v ch cpuclk2 input hi voltage 3.7 v cc a 0.3 v v ol output lo voltage 0.45 v (note 2) v oh output hi voltage 2.4 v (note 3) i cc supply current numclk2 e 32 mhz (4) 160 ma i cc typ. e 95 ma numclk2 e 40 mhz (4) 180 ma i cc typ. e 105 ma numclk2 e 50 mhz (4) 210 ma i cc typ. e 125 ma numclk2 e 66.6 mhz (4) 250 ma i cc typ. e 150 ma i li input leakage current g 15 m a0v s v in s v cc i lo i/o leakage current g 15 m a 0.45v s v o s v cc c in input capacitance 10 pf fc e 1 mhz c o i/o or output capacitance 12 pf fc e 1 mhz c clk clock capacitance 15 pf fc e 1 mhz notes: 1. this parameter is for all inputs, including numclk2 but excluding cpuclk2. 2. this parameter is measured at i ol as follows: data e 4.0 ma readyo y e 2.5 ma error y , busy y , pereq e 2.5 ma 3. this parameter is measured at i oh as follows: data e 1.0 ma readyo y e 0.6 ma error y , busy y , pereq e 0.6 ma 4. i cc is measured at steady state, maximum capacitive loading on the outputs, cpuclk2 at the same frequency as numclk2. 30 30
intel387 tm dx math coprocessor 4.3 ac characteristics table 4.2a. i387 dx/i386 dx interface and execution frequencies frequency (mhz) i386 dx system i387 dx 16-33 execution frequency (mhz) min max 16 mhz 10.0 mhz 22.4 mhz 20 mhz 12.5 mhz 28.0 mhz 25 mhz 15.6 mhz 33.0 mhz 33 mhz 20.6 mhz 33.0 mhz note: the external clock frequencies for the i387 dx and i386 dx are equal to twice the interface and execution frequencies show above. table 4.2b. timing requirements of the execution unit t c e 0 cto a 85 c, v cc e 5v g 5% pin symbol parameter 16 mhz 33 mhz conditions test reference figure min (ns) max (ns) numclk2 t1 period 15 125 2.0v 4.1 numclk2 t2a high time 6.25 2.0v numclk2 t2b high time 4.5 3.7v numclk2 t3a low time 6.25 2.0v numclk2 t3b low time 4.5 0.8v numclk2 t4 fall time 6 3.7v to 0.8v numclk2 t5 rise time 6 0.8v to 2.7v table 4.2c. timing requirements of the bus interface unit t c e 0 cto a 85 c, v cc e 5v g 5% (all measurements made at 1.5v and 50 pf unless otherwise specified) pin symbol parameter 16 mhz 33 mhz conditions test reference figure min (ns) max (ns) cpuclk2 t1 period 15 125 2.0v 4.1 cpuclk2 t2a high time 6.25 2.0v cpuclk2 t2b high time 4.5 3.7v cpuclk2 t3a low time 6.25 2.0v cpuclk2 t3b low time 4.5 0.8v cpuclk2 t4 fall time 6 3.7v to 0.8v cpuclk2 t5 rise time 6 0.8v to 3.7v numclk2/ ratio 10/16 14/10 cpuclk2 readyo y t7 out delay 4 17 4.2 readyo y (1) t7 out delay 4 15 c l e 25 pf pereq t7 out delay 4 25 busy y t7 out delay 4 21 busy y (1) t7 out delay 4 19 c l e 25 pf error y t7 out delay 4 25 d31 d0 t8 out delay 0 37 4.3 d31 d0 t10 setup time 8 d31 d0 t11 hold time 8 d31d0 (2) t12 float time 3 19 31 31
intel387 tm dx math coprocessor table 4.2c. timing requirements of the bus interface unit (continued) t c e 0 cto a 85 c, v cc e 5v g 5% (all measurements made at 1.5v and 50 pf unless otherwise specified) pin symbol parameter 16 mhz 33 mhz conditions test reference figure min (ns) max (ns) pereq (2) t13 float time 1 30 4.5 busy y (2) t13 float time 1 30 error y (2) t13 float time 1 30 readyo y (2) t13 float time 1 30 ads y t14 setup time 13 4.3 ads y t15 hold time 4 w/r y t14 setup time 13 w/r y t15 hold time 4 ready y t16 setup time 7 ready y t17 hold time 4 cmdo y t16 setup time 13 cmdo y t17 hold time 2 nps1 y t16 setup time 13 nps2 nps1 y t17 hold time 2 nps2 sten t16 setup time 13 sten t17 hold time 2 resetin t18 setup time 5 4.4 resetin t19 hold time 3 notes: 1. not tested at 25 pf. 2. float delay is not tested. float condition occurs when maximum output current becomes less than i lo in magnitude. * nom - nominal value 240448 14 note: this graph will not be linear outside of the c l range shown. figure 4.0a. typical output valid delay vs load capacitance at max operating temperature 240448 15 note: this graph will not be linear outside of the c l range shown. figure 4.0b. typical output rise time vs load capacitance at max operating temperature 32 32
intel387 tm dx math coprocessor 240448 16 figure 4.1. cpuclk2/numclk2 waveform and measurement points for input/output a.c. specifications 240448 17 figure 4.2. output signals 33 33
intel387 tm dx math coprocessor 240448 18 figure 4.3. input and i/o signals note: 240448 19 the second internal processor phase following reset high to low transition is ph2. figure 4.4. reset signal 240448 20 figure 4.5. float from sten 34 34
intel387 tm dx math coprocessor table 4.3. other parameters pin symbol parameter min max units resetin t30 duration 40 numclk2 resetin t31 resetin inactive to 1st opcode write 50 numclk2 busy y t32 duration 6 cpuclk2 busy y , error y t33 error y (in) active to busy y inactive 6 cpuclk2 pereq, error y t34 pereq inactive to error y active 6 cpuclk2 ready y , busy y t35 ready y active to busy y active 4 4 cpuclk2 ready y t36 minimum time from opcode write to 6 cpuclk2 opcode/operand write ready y t37 minimum time from operand write to 8 cpuclk2 operand write 240448 21 * in numclk2's ** or last operand note: 1. memory read (operand) cycle is not shown. figure 4.6. other parameters 35 35
intel387 tm dx math coprocessor instruction optional first byte second byte fields 1 11011 opa 1 mod 1 opb r/m sib disp 2 11011 mf opa mod opb r/m sib disp 3 11011 d p opa 1 1 opb st(i) 4 11011 0 0 1 1 1 1 op 5 11011 0 1 1 1 1 1 op 1511 10 9 8 7 6 5 43210 5.0 intel387 tm dx mcp extensions to the intel386 tm dx cpu instruction set instructions for the intel387 dx mcp assume one of the five forms shown in the following table. in all cases, instructions are at least two bytes long and begin with the bit pattern 11011b, which identifies the escape class of instruction. instructions that refer to memory operands specify addresses using the intel386 dx cpu addressing modes. op e instruction opcode, possible split into two fields opa and opb mf e memory format 00e32-bit real 01e32-bit integer 10e64-bit real 11e16-bit integer p e pop 0edo not pop stack 1epop stack after operation esc e 11011 d e destination 0edestination is st(0) 1edestination is st(i) r xor d e 0edestination (op) source r xor d e 1esource (op) destination st(i) e register stack element i 000 e stack top 001 e second stack element # # # 111 e eighth stack element mod (mode field) and r/m (register/memory spec- ifier) have the same interpretation as the corre- sponding fields of the intel386 dx microprocessor instructions (refer to intel386 tm dx microprocessor programmer's reference manual ). sib (scale index base) byte and disp (displace- ment) are optionally present in instructions that have mod and r/m fields. their presence depends on the values of mod and r/m, as for intel386 dx mi- croprocessor instructions. the instruction summaries that follow assume that the instruction has been prefetched, decoded, and is ready for execution; that bus cycles do not require wait states; that there are no local bus hold re- quest delaying processor access to the bus; and that no exceptions are detected during instruction execution. if the instruction has mod and r/m fields that call for both base and index registers, add one clock. 36 36
intel387 tm dx math coprocessor intel387 tm dx mcp extensions to the intel386 tm dx cpu instruction set encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer data transfer fld e load a integer/real memory to st(0) esc mf 1 mod 000 r/m sib/disp 9 18 26 42 16 23 42 53 long integer memory to st(0) esc 111 mod 101 r/m sib/disp 26 54 extended real memory to st(0) esc 011 mod 101 r/m sib/disp 12 43 bcd memory to st(0) esc 111 mod 100 r/m sib/disp 45 97 st(i) to st(0) esc 001 11000 st(i) 7 12 fst e store st(0) to integer/real memory esc mf 1 mod 010 r/m sib/disp 25 43 57 76 32 44 58 76 st(0) to st(i) esc 101 11010 st(i) 7 11 fstp e store and pop st(0) to integer/real memory esc mf 1 mod 011 r/m sib/disp 25 43 57 76 32 44 58 76 st(0) to long integer memory esc 111 mod 111 r/m sib/disp 60 82 st(0) to extended real esc 011 mod 111 r/m sib/disp 46 52 st(0) to bcd memory esc 111 mod 110 r/m sib/disp 112 190 st(0) to st(i) esc 101 11011 st (i) 7 11 fxch e exchange st(i) and st(0) esc 001 11001 st(i) 10 17 comparison fcom e compare integer/real memory to st(0) esc mf 0 mod 010 r/m sib/disp 13 25 34 52 14 27 39 62 st(i) to st(0) esc 000 11010 st(i) 13 21 fcomp e compare and pop integer/real memory to st esc mf 0 mod 011 r/m sib/disp 13 25 34 52 14 27 39 62 st(i) to st(0) esc 000 11011 st(i) 13 21 fcompp e compare and pop twice st(1) to st(0) esc 110 1101 1001 13 21 ftst e test st(0) esc 001 1110 0100 17 25 fucom e unordered compare esc 101 11100 st(i) 13 21 fucomp e unordered compare and pop esc 101 11101 st(i) 13 21 fucompp e unordered compare and pop twice esc 010 1110 1001 13 21 fxam e examine st(0) esc 001 11100101 24 37 constants fldz e load a 0.0 into st(0) esc 001 1110 1110 10 17 fld1 e load a 1.0 into st(0) esc 001 1110 1000 15 22 fldpi e load pi into st(0) esc 001 1110 1011 26 36 fldl2t e load log 2 (10) into st(0) esc 001 1110 1001 26 36 shaded areas indicate instructions not available in 8087/80287. note: a. when loading single- or double-precision zero from memory, add 5 clocks. 37 37
intel387 tm dx math coprocessor intel387 tm dx mcp extensions to the intel386 tm dx cpu instruction set (continued) encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer constants (continued) fldl2e e load log 2 (e) into st(0) esc 001 1110 1010 26 36 fldlg2 e load log 10 (2) into st(0) esc 001 1110 1100 25 35 fldln2 e load log e (2) into st(0) esc 001 1110 1101 26 38 arithmetic fadd e add integer/real memory with st(0) esc mf 0 mod 000 r/m sib/disp 12 29 34 56 15 34 38 64 st(i) and st(0) es cdp0 11000 st(i) 12 26 b fsub e subtract integer/real memory with st(0) esc mf 0 mod 10 r r/m sib/disp 12 29 34 56 15 34 38 64 c st(i) and st(0) es cdp0 1110 r r/m 12 26 d fmul e multiply integer/real memory with st(0) esc mf 0 mod 001 r/m sib/disp 19 32 43 71 23 53 46 74 st(i) and st(0) es cdp0 1100 1 r/m 17 50 e fdiv e divide integer/real memory with st(0) esc mf 0 mod 11 r r/m sib/disp 77-85 101 114 f 81 91 105 124 g st(i) and st(0) es cdp0 1111 r r/m 77-80 h fsqrt i e square root esc 001 1111 1010 97 111 fscale e scale st(0) by st(1) esc 001 1111 1101 44 82 fprem e partial remainder esc 001 1111 1000 56 140 fprem1 e partial remainder (ieee) esc 001 1111 0101 81 168 frndint e round st(0) esc 001 1111 1100 41 62 to integer fxtract e extract components of st(0) esc 001 1111 0100 42 63 fabs e absolute value of st(0) esc 001 1110 0001 14 21 fchs e change sign of st(0) esc 001 1110 0000 17 24 shaded areas indicate instructions not available in 8087/80287. notes: b. add 3 clocks to the range when d e 1. c. add 1 clock to each range when r e 1. d. add 3 clocks to the range when d e 0. e. typical e 52 (when d e 0, 46 54, typical e 49). f. add 1 clock to the range when r e 1. g. 135 141 when r e 1. h. add 3 clocks to the range when d e 1. i. b 0 s st(0) s a % . 38 38
intel387 tm dx math coprocessor intel387 tm dx mcp extensions to the intel386 tm dx cpu instruction set (continued) encoding instruction byte byte optional clock count range 0 1 bytes 2 6 transcendental fcos k e cosine of st(0) esc 001 1111 1111 122 680 fptan k e partial tangent of st(0) esc 001 1111 0010 162 430 j fpatan e partial arctangent esc 001 1111 0011 250 420 fsin k e sine of st(0) esc 001 1111 1110 121 680 fsincos k e sine and cosine of st(0) esc 001 1111 1011 150 650 f2xm1 l e 2 st(0) b 1 esc 001 1111 0000 167 410 fyl2x m e st(1) * log 2 (st(0)) esc 001 1111 0001 99 436 fyl2xp1 n e st(1) * log 2 (st(0) a 1.0) esc 001 1111 1001 210 447 processor control finit e initialize mcp esc 011 1110 0011 33 fstsw ax e store status word esc 111 1110 0000 13 fldcw e load control word esc 001 mod 101 r/m sib/disp 19 fstcw e store control word esc 101 mod 111 r/m sib/disp 15 fstsw e store status word esc 101 mod 111 r/m sib/disp 15 fclex e clear exceptions esc 011 1110 0010 11 fstenv e store environment esc 001 mod 110 r/m sib/disp 103 104 fldenv e load environment esc 001 mod 100 r/m sib/disp 71 fsave e save state esc 101 mod 110 r/m sib/disp 375 376 frstor e restore state esc 101 mod 100 r/m sib/disp 308 fincstp e increment stack pointer esc 001 1111 0111 21 fdecstp e decrement stack pointer esc 001 1111 0110 22 ffree e free st(i) esc 101 1100 0 st(i) 18 fnop e no operations esc 001 1101 0000 12 shaded areas indicate instructions not available in 8087/80287. notes: j. these timings hold for operands in the range l x l k q /4. for operands not in this range, up to 76 additional clocks may be needed to reduce the operand. k. 0 s l st(0) l k 2 63 . l. b 1.0 s st(0) s 1.0. m. 0 s st(0) k % , b % k st(1) k a % . n. 0 s l st(0) l k (2 b sqrt(2))/2, b % k st(1) k a % . 39 39
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intel387 tm dx math coprocessor appendix a compatibility between the 80287 and the 8087 the 80286/80287 operating in real-address mode will execute 8086/8087 programs without major modification. however, because of differences in the handling of numeric exceptions by the 80287 mcp and the 8087 mcp, exception-handling routines may need to be changed. this appendix summarizes the differences between the 80287 mcp and the 8087 mcp, and provides details showing how 8086/8087 programs can be ported to the 80286/80287. 1. the mcp signals exceptions through a dedicated error y line to the 80286. the mcp error signal does not pass through an interrupt controller (the 8087 int signal does). therefore, any interrupt- controller-oriented instructions in numeric excep- tion handlers for the 8086/8087 should be delet- ed. 2. the 8087 instructions feni/fneni and fdisi/ fndisi perform no useful function in the 80287. if the 80287 encounters one of these opcodes in its instruction stream, the instruction will effectively be ignoredenone of the 80287 internal states will be updated. while 8086/8087 containing these instructions may be executed on the 80286/80287, it is unlikely that the exception- handling routines containing these instructions will be completely portable to the 80287. 3. interrupt vector 16 must point to the numeric ex- ception handling routine. 4. the esc instruction address saved in the 80287 includes any leading prefixes before the esc op- code. the corresponding address saved in the 8087 does not include leading prefixes. 5. in protected-address mode, the format of the 80287's saved instruction and address pointers is different than for the 8087. the instruction op- code is not saved in protected modeeexception handlers will have to retrieve the opcode from memory if needed. 6. interrupt 7 will occur in the 80286 when executing esc instructions with either ts (task switched) or em (emulation) of the 80286 msw set (ts e 1or em e 1). if ts is set, then a wait instruction will also cause interrupt 7. an exception handler should be included in 80286/80287 code to han- dle these situations. 7. interrupt 9 will occur if the second or subsequent words of a floating-point operand fall outside a segment's size. interrupt 13 will occur if the start- ing address of a numeric operand falls outside a segment's size. an exception handler should be included in 80286/80287 code to report these programming errors. 8. except for the processor control instructions, all of the 80287 numeric instructions are automati- cally synchronized by the 80286 cpuethe 80286 automatically tests the busy y line from the 80287 to ensure that the 80287 has completed its previous instruction before executing the next esc instruction. no explicit wait instructions are required to assure this synchronization. for the 8087 used with 8086 and 8088 processors, ex- plicit waits are required before each numeric in- struction to ensure synchronization. although 8086/8087 programs having explicit wait in- structions will execute perfectly on the 80286/80287 without reassembly, these wait in- structions are unnecessary. 9. since the 80287 does not require wait instruc- tions before each numeric instruction, the asm286 assembler does not automatically gener- ate these wait instructions. the asm86 assem- bler, however, automatically precedes every esc instruction with a wait instruction. although nu- meric routines generated using the asm86 as- sembler will generally execute correctly on the 80286/80287, reassembly using asm286 may re- sult in a more compact code image. the processor control instructions for the 80287 may be coded using either a wait or no-wait form of mnemonic. the wait forms of these in- structions cause asm286 to precede the esc in- struction with a cpu wait instruction, in the iden- tical manner as does asm86. data sheet revision review the following list represents the key differences be- tween this and the -003 versions of the intel387 tm math coprocessor data sheet. please review this summary carefully. 1. corrected typographical errors. 2. corrected clock ratio ``pin'' name on table 4.2c to numclk/cpuclk. a-1 41

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